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NEWS and PRESS RELEASES

AXILICA Limited releases version 3.0 of  FalconML

28 November 2011. AXILICA announces the latest release of its product FalconML Release 3.0 delivers unique functionality focused on supporting UML modelling for the development of hardware and on providing new capabilities for hardware/software co-design. The new capabilities enable the use of UML-level system constraints to direct behavioural synthesis and determine hardware characteristics.

The new features include support for:

• Integration of external IP
• A number of MARTE modelling constructs needed for the development of embedded systems including,

• Allocation of model elements to architectural resources
• Non-functional constraints using the MARTE Value Specification Language
• Interfaces to external memories described using MARTE.

• Pointer (C/C++) access to external memories

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AXILICA Limited Contributes to ENOSYS Advanced Design Flow

18 July 2011. AXILICA has implemented and delivered a series of enhancements to its FalconML product to support the initial version of the ENOSYS design flow. This design flow delivers a UML to hardware flow for the implementation of embedded systems comprised of hardware and software on a target FPGA platform.

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AXILICA Limited releases version 2.0 of FalconML

6 June 2011. AXILICA announces the latest release of its product FalconML. Release 2.0 delivers new functionality that increases support for the design of embedded systems. This specifically encompasses modelling tools, programming languages and FPGA platforms frequently used in embedded design methodologies.

The new features include support for:

• Hardware/software co-design using the Xilinx MicroBlazeTM processor;
• C as an action language in UML models and generation of C code where relevant;
• A single-threaded option for generating software components in hardware/software co-design;
• UML modelling with Softeam ModelioTM and Atego Artisan StudioTM; and
• Requirements traceability from UML models (objects and classes) to code: C/ C++ for software and RTL /TLM  for hardware.

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AXILICA  Moves into New Offices

10 February 2011. AXILICA Limited has moved to new offices in the Holywell Business Park, Loughborough.  The move maintains AXILICA’s links with the Loughborough Innovation Centre and provides AXILICA with new facilities needed to expand product development.  There are no changes to our phone numbers!

AXILICA and Abstract Solutions Collaborate to Provide Advanced UML-based Solutions and Services

16 November 2010. AXILICA Limited announced today the signing of a collaboration agreement with Abstract Solutions Limited designed to deliver the UML® training, consultancy and modelling expertise offered by Abstract Solutions to companies adopting Axilica’s UML-based behavioural synthesis solutions.

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AXILICA to exhibit at IBM Software Innovate 2010 – London, 12 October 2010.

AXILICA will be demonstrating the advanced capabilities of its product, FalconML, at Innovate 2010 The Rational Software Conference (London, 12 October 2010). Innovate 2010 is the premier software and systems event that provides IBM’s customers with the opportunity to hear from IBM speakers, other customers, industry experts and IBM Business Partners.

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FalconML  White Paper is Available Now

2 August 2010.  A new white paper describing the technical foundations of AXILICA’s FalconML product is available from the AXILICA’s website. This white paper describes the benefits of using UML for modelling hardware structure and behaviour; the key concepts implemented in the behavioural synthesis engine in FalconML; and some of the techniques used by AXILICA to ensure the generation of HDL (Verilog, VHDL) descriptions that result in efficient hardware.

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AXILICA Limited to exhibit at ESC Silicon Valley 2010; 26th – 29th April 2010, San Jose, USA.

AXILICA will exhibit its model-driven UML-based behavioural synthesis product,  ‘FalconML’, at ESC Silicon Valley. FalconML enables the of use of industry-standard SysML and UML modelling tools for the implementation of complex hardware devices, such as FPGAs and ASICs, within advanced embedded systems.

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AXILICA Limited and SELEX Galileo
Collaborate on a new Methodology for Advanced Product Development

26 April 2010. AXILICA announced today that SELEX Galileo Ltd has selected AXILICA’s FalconML as an enabling technology for aspects of an innovative UML-based embedded systems development methodology, which will offer a model-driven approach for the rapid development and enhanced through-life support of EW systems."

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AXILICA Limited secures €495K grant from European Commission FP7 program
to enhance FalconML to support MARTE and multi-core processors

26 April 2010. AXILICA announced today that in partnership with other European companies - including Thales Communications, Softeam (France); Loughborough University (UK); and University of Peloponnese and Intracom (Greece) - it has secured a total grant of €2.6M from the European Commission FP7 program for the ENOSYS project (intEgrated modelliNg and synthesis tOol flow for embedded SYStems design).

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AXILICA Limited releases version 1.2 of FalconML.

AXILICA announces the latest release of its product  ‘FalconML’. Release 1.2 includes a number of enhancements and new functionality designed to increase FalconML’s support for the development of advanced embedded systems and complex hardware.

• The new features include support for:
• Hardware/software co-design using the Altera Nios II CPU and Avalon interconnect;
• The FreeRTOS/OpenRTOS embedded OS, in addition to pre-existing support for POSIX;
• UML source-level debugging/profiling for generated hardware descriptions and SystemC; and SystemC TLM 2.

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AXILICA Limited demonstrates FalconML

at Embedded System Conference Automation Conference (ESC) 22nd - 23rd September 2009, Boston , USA.

AXILICA Limited exhibit its state-of-the-art behavioural synthesis product, ‘FalconML’, at the ESC Conference in Boston. FalconML enables the transformation of UML system-level descriptions, captured in standard UML modelling tools, into an RTL hardware description (VHDL, Verilog) ready for implementation on an FPGA or ASIC. FalconML also includes an option to generate SystemC for high-performance functional simulation.

  

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AXILICA Limited demonstrates FalconML

at Design Automation Conference (DAC) 7th – 14th June 2008, Anaheim, USA.

Innovative UML flow from AXILICA Limited exhibits at DAC’08. AXILICA Limited will exhibit ‘FalconML’, a state-of-the-art behavioural synthesis product for large-scale FPGA and ASIC system synthesis. This innovative flow starts from UML and results in a fully-scheduled and allocated, technology independent netlist ready for input to existing RTL flows. FalconML will be demonstrated at the Design Automation Conference www.dac.com from the 7th to the 13th June 2008, Anaheim, USA.

  

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AXILICA Limited demonstrates FalconML

at DATE conference on 10th – 14th March 2008, Munich, Germany.

AXILICA Limited demonstrates ‘FalconML’ a state of the art product for behavioral synthesis of hardware designs from UML that targets FPGAs or ASICs. FalconML  is a powerful new tool developed by Axilica to deliver behavioural synthesis of FPGA or ASIC-directed hardware designs from UML. AXILICA Limited demonstrates FalconML at DATE conference on 10th – 14th March 2008, Munich, Germany.

  

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