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AXILICA Limited releases version 3.0 of FalconML

AXILICA announces the latest release of its product FalconML. Release 3.0 delivers unique functionality focused on supporting UML modelling for the development of hardware and on providing new capabilities for hardware/software co-design. The new capabilities enable the use of UML-level system constraints to direct behavioural synthesis and determine hardware characteristics.

The new features include:

• Integration of external IP.

FalconML supports the integration of external IP (hardware or software) not developed with FalconML. Individual classes in a UML model can be marked as FalconML-generated or non-FalconML generated, allowing the use of FalconML to generate descriptions for some targets, while using non-FalconML IP for other targets. This could be used, for example, to generate a SystemC description with FalconML but hand-implement the equivalent VHDL.

• A number of MARTE modelling constructs needed for the development of embedded systems including,

• Allocation of model elements to architectural resources

The use of MARTE allocations is now supported for partitioning hardware and software in the UML models. The MARTE allocation syntax is an OMG® standard for the allocation of model elements to architectural resources.

• Non-functional constraints using the MARTE Value Specification Language

FalconML implements support for non-functional constraints specified using the MARTE Value Specification Language (VSL) representation. These include constraints on hardware performance and resource utilisation.

• Interfaces to external memories described using MARTE

Interfaces to external memories can be described using MARTE and memories can be accessed using the standard pointer notation in the C/C++ action language. (see below)

MARTE is the UML Profile for the Modelling and Analysis of Real-Time and Embedded systems developed by the OMG. Support for selected MARTE modelling constructs is essential to the design flows being developed by AXILICA in conjunction with a number of its customers and partners.

• Pointer (C/C++) access to external memories

FalconML adds support for mastering external memories. Interfaces to external memories are modelled using MARTE, and memories can be accessed using the standard pointer notation in the C/C++ action language. Two interconnect standards are supported: the CoreConnect Processor Local Bus (PLB) interconnect commonly used on Xilinx FPGAs and Altera's Avalon interconnect.

Many of the new capabilities launched in FalconML 3.0 have been implemented as part of AXILICA’s participation in the ENOSYS project. ENOSYS is a project funded under the European Commission’s FP7 Program and focuses on an integrated design flow including advanced system modelling, design space exploration and hardware/software synthesis of SoC systems. In close collaboration with its partners in the ENOSYS project, AXILICA has been developing new capabilities in FalconML to meet the technical objectives of the project.

About AXILICA

AXILICA Limited is a private company with headquarters in Loughborough, United Kingdom. The company is shaping the future of systems development by providing advanced synthesis products supporting hardware-software co-design and rapid development of hardware (FPGAs and ASICs).

For further information on AXILICA or any of its products, please contact:

 AXILICA Limited

 Charnwood Building

 Holywell Park

 Ashby Road

 Loughborough

 LE11 3AQ

 United Kingdom

 Email:     info@axilica.com

 Tel:        +44 (0)1509 227131

 Fax:       +44 (0)1509 276263

 Website: www.axilica.com

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