Axilica Limited - All Rights Reserved.

London, United Kingdom,  October 23rd 2009.

 

AXILICA Limited releases version 1.2 of  of FalconML
 

AXILICA announces the latest release of its product FalconML. Release 1.2 includes a number of enhancements and new functionality designed to increase FalconML’s support for the development of advanced embedded systems and complex hardware.

 

The new features include:

 

• Support for hardware/software co-design using the Altera Nios II CPU and Avalon interconnect.

In addition to existing support for a number of generic and vendor specific CPUs incorporated in previous product releases, FalconML now supports Altera’s Nios II CPU and Avalon interconnect, expanding support for market leading product development capabilities required by AXILICA’s customers.

 

• Support for the FreeRTOS/OpenRTOS embedded OS, in addition to pre-existing support for POSIX.

FalconML now facilitates the use of the FreeRTOS/OpenRTOS real-time OS delivering the benefits of its ease of use, widespread porting to different platforms and support for multi-tasking. FalconML continues to support POSIX compliant OS’s ported to large number of CPU’s used in advanced embedded systems.

 

• Support for UML source-level debugging/profiling for generated hardware descriptions and generated SystemC.

FalconML provides new facilities to debug and profile simulation results at the UML level of abstraction. For hardware descriptions generated by FalconML, RTL simulation results can be back-annotated onto the source UML-level constructs for debugging and/or profiling. For SystemC descriptions, the new FalconML features enable UML-level profiling from simulations of the generated SystemC.

 

• Support for SystemC TLM 2.

SystemC TLM 2 introduces an industry standard aimed at ensuring portability of SystemC descriptions and enabling faster system simulation at higher levels of abstraction. FalconML version 1.2, with its support for TLM 2, facilitates the capture of key intellectual property in UML and the creation of verified SystemC descriptions of essential IP blocks and sub-systems.

 

• Enhancements to the RTL code (VHDL,Verilog) generated by FalconML to extend support for advanced hardware design.

 

Release 1.2 delivers advanced functionality required by AXILICA’s customers in the military, aerospace, telecommunications and consumer electronics markets to continue advanced product development with reduced development time scales, reduced product development costs and higher product quality.

 

 

About AXILICA

AXILICA Limited is a private company with headquarters in Loughborough, United Kingdom. The company is shaping the future of systems development by providing advanced synthesis products supporting hardware-software co-design and rapid development of hardware (FPGAs and ASICs).

 

For further information on AXILICA or any of its products, please contact:

 

 AXILICA Limited

 Loughborough Innovation Centre

 Epinal Way,

 Loughborough,

 LE11 3EH,

 United Kingdom

 

 Email:     info@axilica.com

 Tel:        +44 (0)1509 227131

 Fax:       +44 (0)1509 276263

 Website: www.axilica.com

 

Less...

PRESS RELEASE