Axilica Limited - All Rights Reserved.

PRESS RELEASE

London, United Kingdom,  June 2nd 2008.

 

AXILICA Limited demonstrates FalconML

at Design Automation Conference (DAC) 7th – 14th June 2008, Anaheim, USA.

 

 

Innovative UML flow from AXILICA Limited exhibits at DAC’08

 

 

AXILICA Limited will exhibit ‘FalconML’, a state-of-the-art behavioural synthesis product for large-scale FPGA and ASIC system synthesis. This innovative flow starts from UML and results in a fully-scheduled and allocated, technology independent netlist ready for input to existing RTL flows. FalconML will be demonstrated at the Design Automation Conference www.dac.com from the 7th to the 13th June 2008, Anaheim, USA.

 

FalconML radically improves designer productivity, allowing electronic chip design companies to:

 

• Construct complex systems with considerably reduced development times
• Minimise product development costs
• Reach markets ahead of competitors
• Rapidly add key differentiating features.

 

AXILICA Limited will demonstrate FalconML in booth #1373 during the exhibition and customers are encouraged to pre-register at www.axilica.com to arrange a one-on-one meeting with the FalconML team.

 

In addition, AXILICA Limited will give a talk on ‘The UML-based design of a hardware H264/MPEG4 AVC decompression core’ at the 5th International UML for SoC Design Workshop on 7th June 2008. A demonstration of FalconML will also be given as part of this session.

 

AXILICA Limited is currently working with customers in the Military, Telecommunications, and Consumer Electronics industries. We are looking forward to working with additional customers in these or other sectors.

 

FalconML is a front-end EDA tool that initiates the design process at the UML specification level.  It enables true software/hardware partitioning and delivers an output compatible with all EDA back-end flows.  The advanced behavioural synthesis engine in FalconML provides routes from UML to both SystemC (for high-performance functional simulation) and to RTL (targeting both FPGAs and ASICs). Silicon IP generated by FalconML can integrate with legacy IP through direct control of design interfaces, allowing such IP to be utilised in new high-performance large-scale VLSI solutions, while taking advantage of the accelerated design process offered by FalconML.

 

Why use FalconML?

 

• FalconML automates the flow from specification capture to chip while shortening time to market
   
• FalconML gives a common starting point for hardware and software design, simplifying co-design and partitioning decisions
   
• FalconML integrates easily with existing tools and processes
   
• For software design companies, FalconML gives low cost of entry into hardware design, while end-products operate faster, consume less power and can be miniaturized

 

AXILICA Limited provides products and services to support the rapid development of electronic systems.

 

 

Product Availability

FalconML is available now for evaluation and/or purchase.

 

 

About AXILICA

AXILICA Limited is a spin-out from Loughborough University’s Electrical & Electronic Engineering Department. Initial funding was provided by IPSO Ventures  and The Lachesis Fund, with Loughborough University Enterprises Limited as an additional shareholder.

 

 

Technical Contact

 

 Jitu Choudhury, Vice President, Business Development

 Axilica Limited

 Loughborough Innovation Centre

 Epinal Way,

 Loughborough,

 LE11 3EH,

 United Kingdom

 

 E-mail: jitu@axilica.com

 

 Tel: +44 (0)1509 - 227 - 131

 Dir: +44 (0)1509 - 225 - 834

 

 http://www.axilica.com

 

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